NXP Semiconductors /LPC11D14 /CT32B0 /EMR

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Interpret as EMR

31 2827 2423 2019 1615 1211 87 43 0 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (EM0)EM0 0 (EM1)EM1 0 (EM2)EM2 0 (EM3)EM3 0 (DONOTHING)EMC0 0 (DONOTHING)EMC1 0 (DONOTHING)EMC2 0 (DONOTHING)EMC3 0RESERVED

EMC0=DONOTHING, EMC2=DONOTHING, EMC3=DONOTHING, EMC1=DONOTHING

Description

External Match Register (EMR). The EMR controls the match function and the external match pins CT32B0_MAT[3:0].

Fields

EM0

External Match 0. This bit reflects the state of output CT32Bn_MAT0, whether or not this output is connected to its pin. When a match occurs between the TC and MR0, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[5:4] control the functionality of this output. This bit is driven to the CT32B0_MAT0/CT16B1_MAT0 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

EM1

External Match 1. This bit reflects the state of output CT32Bn_MAT1, whether or not this output is connected to its pin. When a match occurs between the TC and MR1, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[7:6] control the functionality of this output. This bit is driven to the CT32B0_MAT1/CT16B1_MAT1 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

EM2

External Match 2. This bit reflects the state of output CT32Bn_MAT2, whether or not this output is connected to its pin. When a match occurs between the TC and MR2, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[9:8] control the functionality of this output. This bit is driven to the CT32B0_MAT2/CT16B1_MAT2 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

EM3

External Match 3. This bit reflects the state of output CT32Bn_MAT3, whether or not this output is connected to its pin. When a match occurs between the TC and MR3, this bit can either toggle, go LOW, go HIGH, or do nothing. Bits EMR[11:10] control the functionality of this output. This bit is driven to the CT32B0_MAT3/CT16B1_MAT3 pins if the match function is selected in the IOCON registers (0 = LOW, 1 = HIGH).

EMC0

External Match Control 0. Determines the functionality of External Match 0.

0 (DONOTHING): Do Nothing.

1 (CLEAR): Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

2 (SET): Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

3 (TOGGLE): Toggle the corresponding External Match bit/output.

EMC1

External Match Control 1. Determines the functionality of External Match 1.

0 (DONOTHING): Do Nothing.

1 (CLEAR): Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

2 (SET): Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

3 (TOGGLE): Toggle the corresponding External Match bit/output.

EMC2

External Match Control 2. Determines the functionality of External Match 2.

0 (DONOTHING): Do Nothing.

1 (CLEAR): Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

2 (SET): Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

3 (TOGGLE): Toggle the corresponding External Match bit/output.

EMC3

External Match Control 3. Determines the functionality of External Match 3.

0 (DONOTHING): Do Nothing.

1 (CLEAR): Clear the corresponding External Match bit/output to 0 (CT32Bn_MATm pin is LOW if pinned out).

2 (SET): Set the corresponding External Match bit/output to 1 (CT32Bn_MATm pin is HIGH if pinned out).

3 (TOGGLE): Toggle the corresponding External Match bit/output.

RESERVED

Reserved, user software should not write ones to reserved bits. The value read from a reserved bit is not defined.

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